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Answered) The last major component is the pseudo-random number state machine.


Can anyone help me with the truth table and state table.


The last major component is the pseudo-random number state machine. In each clock cycle, it uses the previously computed digit and S to compute a digit in the range [0, 9] to be written into the register file. Its next state logic is defined as follows. Let f(t) represent the previously generated digit and S be the current input from the shift register:1.png

Note that this arithmetic is performed with respect to mod 10 so that the values remain in the range [0, 9]. (For example, if f(t) = 2 and S = 1, the next number f(t+1) will be 5).

The described use case will cycle through the register file twice, since the seed is 8 bits while the register file contains only 4 registers.

Sample Case: The seed 11000011 will yield the sequence 4, 7, 9, 3, 1, 7, 0, 3 with final register values R0 = 1, R1 = 7, R2 = 0, R3 = 3.

 


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