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(Solved) Homework 4: ADCs ECE 5540 Due May 10th This homework will involve looking at, and choosing component values for several kinds of ADC, and verifying...

Please see the attached matlab project need to be done

Homework 4: ADCs

ECE 5540

Due May 10th

This homework will involve looking at, and choosing component values for several kinds of ADC, and

verifying them in MATLAB, using custom code supplied. There will be no Cadence work (youâ€™re

welcome). However, you will need to get used to my MATLAB script. This involve a shell script

(ADC_shell.m), 4 ADC models (flash.m, SAR.m, cyclic.m, sig_delt_1st_order.m), and two analysis

functions (INLDNL.m, spect.m).

All of these designs use capacitor ratios and comparators, we will assume the following:

1) Inputs are between 0V and 1V, and fed-back bits are 0V and 1V

2)

3)

4)

5)

6)

7)

8) 9) Two capacitors of value Co are matched with a 1-Ïƒ value = 1 âˆ™ âˆš â„800.

Comparators can be multiplied in size by an integer M (lego-style)

Unit comparators consume 10fJ/compare

Unit comparators have a 1-Ïƒ input referred offset voltage = 10 and an input referred

noise of 0.8mVrms (applied to each compare).

Comparators can settle in 2ns.

OTAs, where needed, can settle in 5ns, but consumes energy per cycle of 10ns*gm*0.5V2.

Also, assume capacitors have a density of 1fF/um2 (so area equals the total capacitance, in fF

times 1um2), assume a unit comparator take 10um2, (so total area equal 10um2*M*(# of

comparators)), and assume OTA area goes as gm*2x105 um2 (so if gm=1mS, area=200um2)

Assume OTAs are ideal transconductances . In all cases we are interested in getting> 95% yield. Remember that 67% of cases are within 1Ïƒ, 95% of

cases are within 2Ïƒ, 99.7% are within 3Ïƒ, and 99.99% are within 4Ïƒ.

Note that all ENOB analyses only look at inputs from 50mV to 950mV: you will see why. 1) Flash ADC: the design is shown.

a. For an N-bit Flash, how many

comparators do you need?

b. What is the maximum sample rate

of this converter (assuming the

comparators are what limit

conversion time)?

c. What is the likely 1-Ïƒ distribution of

DNL, in LSBs, in terms of N and M?

d. What is the likely 1-Ïƒ INL for the

middle code, due to the C- ladder as

well as from the comparator, in

terms of N, Co and M?

e. For an 8-bit Flash, if you want the

worst DNL to be less than 2LSB with

95% probability, how big do your

comparators need to be (what is

M)? Note: for K comparators, the

overall probability of the circuit

passing spec is the probability of one

comparator passing spec (Ppass) to

the Kth power. So: (Ppass)K>95%. For this case, how much total energy will you require for one

conversion?

f. Now, we will run some simulations of this in MATLAB. Ensure all the required .m files are in

your working directory, and run ADC_shell. Select â€œflashâ€ from the menu. Start with the

default design parameters (Co=4fF, M=1, N=8), use a ramp input (ramps from 0V to 1V).

Include the resulting plot with your solution, and estimate the worst case INL and DNL, and the

associated ENOB.

g. Repeat, but now for a sinusoidal input (default values for magnitude and frequency). Plot, and

estimate the SFDR from the spectrum.

h. To get a sense for the statistical behavior of these properties, run the same ADC design through

a â€œbatchâ€ simulation. This runs a ramp and sinewave through 100 instantiations of the ADC (A

Monte-Carlo simulation: it will take a minute of two to run). What are the worst case INL, DNL

and SFDR? Also, looking at Figure 3, what is the ENOB (based on worst INL, DNL, RMS error

(INL) and from the spectrum)? Do the various ENOBs seem to correlate with each other?

i.

Now, using your answers from parts d and e as a starting point, choose Co, M and N to build a

flash converter with ENOB >6dB by all measures of ENOB, across a batch simulation. You

should also seek to minimize power consumption (based on the number and size of the

comparators) and area (based on the number and size of the comparators and capacitors). For

this design, fill out the â€œflashâ€ column at the end of the HW. Compute energy/conversion and

area, and report the SFDR. (donâ€™t spend too much time trying make this perfect!!)

j.

Repeat, but now try to get > 8bits ENOB. What do you need to scale, and by how much? 2) Charge redistribution SAR-ADC: the schematic is shown.

a. For a 5-bit design, assuming ideal components (no mismatch or offsets) walk through the

conversion steps for Vin = 0.8V, similar to what we did in class (just fill out the table below).

b. Repeat this analysis, but with the comparator having a 100mV offset (as if Vref=0.9V). What is

the general impact of offset errors on the output? How would this limit your input range? c. Now, for an N-bit converter, how many unit capacitors are there? How many comparators?

d. Assuming the compare operation is what limits your speed, what is the maximum sampling

rate of the converter?

e. What will your total energy per conversion be, in terms of N and Co (this should include both

energy for the comparator and 2/3*Ctotal*1V2 for cycling the capacitors.

f. What will be the 1-Ïƒ DNL on the worst symbol-transition, in terms of N and Co?

g. In MATLAB, now, do a quick simulation to confirm your results from part a. Choose â€˜SARâ€™, set

N=5, and set both Co and M to 100 (to avoid random errors). Now choose â€œone voltageâ€ for

your input, and make it 0.8V. confirm you get the same bits and Vx.

h. Next, simulate the SAR again, this time with default parameters,( N=8, Co=4, M=1), and a

ramp input. What is the worst case DNL and INL? At which codes do they occur?

i. Now, run a batch simulation on the SAR, again with default values. Which codes show the

worst DNL and INL? What is the worst case SFDR. What is the worst case ENOB?

j. Based on parts b and c, design N, M and Co for ENOB>6bits, by all measures under a batch

simulation, while trying to minimize area and energy. For this design, fill out the â€œSARâ€ column

at the end of the homework. Compute the energy per conversion and area, and report the

SFDR. (donâ€™t spend too much time on this!!)

k. Repeat, but now try to get 8bits ENOB. 3) Cyclic ADC. This includes the option for a gain calibration on the gain stage.

a. Similar to SAR: For a 5-bit design, assuming ideal components (no mismatch or offsets) walk

through the conversion steps for Vin = 0.8, similar to what we did in class (just fill out the table

below: use excel or a calculator). b. Compute the 1-Ïƒ gain error (N1/NF) based on N1, NF and Co.

c. What gm does your OTA need to settle (10 time constants in 10ns), your answer should be in

terms of Co and N1.

d. What will your maximum sampling rate be, given the comparator speed and OTA settling.

e. What is your total energy per conversion, in terms of N, N1 and Co?

f. Confirm you results from part a in MATLAB: Choose â€˜cyclicâ€™, set N=8, and set both Co and M

to 100 (to avoid random errors), N1=20, NF=10. For calibration choose â€œNoâ€. Now choose

â€œone voltageâ€ for your input, and make it 0.8V. do the first 5 iterations match?

g. Now perform 4 ramp simulations: Choose â€˜cyclicâ€™, set N=8, and leave Co, M at default. Now try

four cases: (N1=20, NF=10), with Calibration off and on, (N1=18, NF=10), (N1=22, NF=10) each

with calibration on. Compare the â€œramp outputâ€ plots as well as INL and DNL. What do you

observe?

h. Now perform a batch simulation: Choose â€˜cyclicâ€™, Leave all parameters at default values and no

calibration. The results should be pretty bad. Are the different measures of ENOB correlated

now? Explain what would cause them to be correlated, and the ENOB to be so variable?

Repeat with calibration =yes. Does it improve?

i. Based on parts b and c, design N (number of cycles), M, Co, N1 and NF, for ENOB>6bits, by all

measures under a batch simulation (calibration=yes), while trying to minimize area and energy.

For this design, fill out the â€œcyclicâ€ column at the end of the homework. Compute the energy

per conversion and area, and report the SFDR. (donâ€™t spend too much time on this!!)

j. Repeat, but now try to get 8bits ENOB. 4) Sigma Delta:

a. What is the quantization noise shaping and signal gain you would expect from this

circuit? Write in terms of â€œAâ€, N1, N2 and NF.

b. What gm does your OTA need to settle (10 time constants in 10ns), your answer should

be in terms of Co, N1 and N2.

c. If you have an oversampling ratio (2Â·BW/Fs)=R, how much energy do you consume per

effective sample, in terms of M, Co, N1, N2, and R. If you are limited in speed by the

comparator and OTA, what is you maximum effective sampling rate?

d. Run the MATLAB script and choose â€œsigma-deltaâ€, leave all settings at default (which

means R=100), and choose â€œsingle voltageâ€, and set it to: 0.1, 0.4 and then 0.9. What do

you observe about the bits out and Vx in each case? Does it make sense?

e. Now, run a sinusoidal simulation, again with defaults. You will see both the basic

spectrum, and the spectrum after filtering and decimation (by a factor of 2*BW/fs).

Does the shape of the noise match you expectations from part a?

f. Finally choose Co, M, N1, N2, NF Bandwidth and Fs to achieve an ENOB >8bits (based

only on SNR). Note: do the other measures of ENOB match? What is your area and

energy per effective sample? Fill out the sigma-delta column on the table. (donâ€™t spend

too much time on this!!)

g. Repeat, but now try to get 10bits ENOB based on SNR. What did you need to scale? FLASH

N

Co

M

# comp

# caps

# comp/conv

Fs max

J/conv.

Area

N1

N2

NF

BW

ENOB INL

ENOB DNL

ENOB SNR

SFDR SAR 6b 8b 6b 8b N/A

N/A

N/A

N/A N/A

N/A

N/A

N/A N/A

N/A

N/A

N/A N/A

N/A

N/A

N/A Cyclic

6b 8b N/A N/A N/A N/A sigma-delta

8b

N/A 10b

N/A

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