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(Solved) My Tiny Processor -- Design of a single-cycle 16-bit Processor Machine Organization: Instruction memory and data memory are half-word addressed (i....


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My Tiny Processor -- Design of a single-cycle 16-bit Processor
Machine Organization:
Instruction memory and data memory are half-word addressed (i.e. each location contains a 16-bit
data. Memory address is also 16-bit long. A register file having 2 read-ports and 1 write port
consists of a set of 16 registers each of 16-bit. Also available are some special registers such as
PC, a number of ALUs and MUXs of various sizes and so on. Assume ALU only supports two
operations (add, or) so a1-bit control signal enough for ALU operation, assuming 0 (add), 1 (or).
Thus, a signal from main control unit is good for control ALU and no separate ALU control unit
needed.
Instruction Format:
Four instructions are to be implemented. These four instructions have the same instruction type:
4-bit opcode; 4-bit register field
Opcode
Rs
Rt
Rd
Add
Or
Lw
Sw Rd, Rs, Rt:
Rd, Rs, Rt:
Rd, Rs, Rt:
Rd, Rs, Rt: opcode 0001, performs Reg[Rd] <- Reg[Rs] + Reg[Rt]
opcode 0011, performs Reg[Rd] <- Reg[Rs] or Reg[Rt]
opcode 0100, performs Reg[Rd] < -Mem[Reg[Rs]] #Note: Rt not used
opcode 0101, performs Mem[Reg[Rs]] <- Reg[Rd] #Note: Rt not used Project Requirements:
(1) Design a simple datapath with one main control unit (similar to Figure 4.17) but without
ALU control unit aimed at executing the above instructions only.
(2) Show the truth table (similar to Figure 4.18) to list values of the control signals for each
of the instructions respectively.
(3) Assume registers and memories have the following initial values respectively, and PC
initialized as 0, trace your datapath and show the output of the major functional units.
Initial register values (in hex notation)
R0
0000
R1
0003
R2
0005
R3
0006
R4
0008
R5
000A
R6
000C
R7
000E
R8
1000
R9
1003
R10
1005
R11
1006
R12
1008
R13
100A
R14
100C
R15
100E
Initial instruction memory content:
The following four instructions are loaded into the instruction memory, starting
from memory address 0.
Lw
R6, R1, R5
Lw
R7, R2, R4
Add
R8, R6, R7
Or
R9, R8, R5
Sw
R9, R10, R2
Initial data memory content: (in hex notation) D[0] = 0A00, D[1] = 0A02, D[2] = 00A0, D[3]=00A2, D[4] = B000, D[5]=B002
Rest of memory locations are initialized to be 0.
Submission Requirements:
(1) A hardware diagram of your design
(2) A truth table for the control unit
(3) Hand trace output (fill in the following table with data in hexadecimal format):
Cycles
Output (if not on critical path, put x – don’t care)
Reg read
Reg read
Instruction Memory ALU
Data memory
data #1
data #2
(only indicate the
result (for lw: data read out;
location read)
for sw: memory
content updated)
1
2
3
4
5
(4) Values in registers after execution.
(5) Show the memory contents that were updated at the execution.

 


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